This invention relates generally to data communications, and, more particularly, to high-speed serial data recovery.
There is a trend in the industry to transition from typically lower-speed parallel interfaces to higher-speed serial interfaces in order to reduce system cost and improve performance. Serial interfaces commonly have a lower voltage requirement as well as a lower pin count. Additionally, serial interfaces typically use smaller, easier-to-route cables that result in reduced cable clutter.
High-speed serial interfaces generally employ clock recovery techniques to sample the incoming data. As such, high-speed serial interfaces are available to avoid the need for a separate wire for clock signaling. One technique becoming more prevalent in high-speed serial data recovery is oversampling, which may be used to extract data from an incoming serial bit stream.
Oversampling may result in lower cost, may be easier to integrate, and may have a faster lock time than other traditional analog techniques. Oversampling generally entails sampling data at a faster rate than the rate of the incoming data to extract the clock and data from the incoming data.
However, when oversampling, a mismatch between a receiver clock and a transmitter clock may result in either extra or fewer sampled bits at the output, depending on whether the receiver clock is faster or slower than the transmitter clock. That is, in one instance the frequency of the receiver clock may be slightly slower than the transmitter clock, while in another instance the receiver clock may be slightly faster. As a result of the frequency mismatches, in some cases one or more bits may be skipped or counted twice because the receiver clock may be faster or slower than the transmitter clock.
In some instances, elasticity registers have been used to account for the skipped or twice-counted sampled bits resulting from clock mismatches. However, such registers are generally of a finite size and, therefore, tend to have limited capacity to address the clock mismatch problem.
The use of spread spectrum clocking (SSC) in serial communications interfaces may exacerbate the above-mentioned clock mismatch problem during high-speed data recovery. SSC entails slightly varying the clock frequency at a relatively slow rate to spread any resulting emissions over a broad range of frequencies so that no one frequency in general violates applicable standards. In some instances, both the receiver clock and the transmitter clock may have varying frequencies. While the frequency variance may help to satisfy applicable standards, it may, in some cases, worsen the clock mismatch problem, thereby adversely affecting the serial data recovery process.
Thus, there is a need for an improved high-speed serial data recovery process.